What is a Magnetic Rotary Encoder?

Well, an encoder is basically what it sounds like. It’s a device that takes in some signal and translates (encodes) it into codes. A rotary encoder takes angular position and encodes into either an analog or digital set of codes. Basically it translates the angle of rotation of something into a useful number, either represented as an analog voltage or a binary number for digital encoders.

Typically, rotary encoders are somehow affixed to a rotating object, like a rotating shaft, and are used for counting revolutions, or for measuring angular velocity. There are some instances where attaching something directly to the shaft is for some reason undesirable, hence the creation of the magnetic rotary encoder. By affixing a magnet to the rotating shaft, and measuring the changing magnetic field due to the rotation of the magnet, we can determine the position of the shaft without disturbing the shaft (sans the addition of the magnet).

This project arose out of the Force Controlled Actuator project. We were using the Austria Microsystems AS5040 , which is a magnetic rotary encoder in a small, surface-mount package. Due to the design of the actuator, we needed to allow for the shaft to move laterally, as well as rotate, so we needed to have a contact-less encoder.

Kevin Sihlanick, one of my actuator project teammates, and I were curious as to how the AS5040 worked, so we decided to build a simple version of it for our MADVLSI class (MADVLSI = Mixed Analog and Digital VLSI).

Basic Approach

Our basic building block was the MAGFET, also known as the Magnetic Field Effect Transistor. Implemented in CMOS technology, it’s essentially a split-drain nMOS transistor that’s longer than a unit transistor. By setting a bias voltage on the gate of the MAGFET, we can force a bias current in the transistor. Of course, a current means moving electrons. If we add a magnetic field, then we have a force on the electrons as described by the standard equation:


This has the effect of forcing the electrons to favor one branch of the split drain of the MAGFET. By measuring the difference in current in the two branches, we can determine the polarity, and relative strength of the magnetic field.

If we have an array of MAGFETs, we can then determine the field characteristics over the area of the array.

Detailed Approach

We decided to adopt the approach outlined by Nakano, K., Takahashi, T., and Kawahito, S. in their 2005 paper A CMOS rotary encoder using magnetic sensor arrays published in IEEE Sensors Journal Vol. 5, pp. 889-894. The essential idea was to build four linear arrays of MAGFETs and outline a box with the four arrays as shown in the figure. The axis of rotation is through the center of the MAGFET array structure.

MAGFET array structure
Figure 1. MAGFET Array Structure

The central tenet here is that if the magnetic field is aligned along the dark line as shown in the figure. The idea here is that due to rotational position of the magnetic field, the branch of the split drain that the majority of the current flows through will switch to the other branch upon crossing the line of the magnetic field. If we encode the majority current branch as a bit, i.e. we set a bit to 1 if the current is primarily in the left branch and 0 if the current is primarily in the right branch, we can simply look at the point in the linear array at which the bits flip from 1 to 0 or vice versa. By examining all four branches together and doing some simple geometry, we can extract the rotation angle of the magnet. Of course, we have to worry about noise and so forth, so we need some way of filtering the noise and thus prevent a pattern where the bitstring flips from 1 to 0 back to 1 again, or vice versa.

Spatial Averager

In order to accomplish this, we chose to use a spatial averager. Since there are two branches in the split-drain MAGFET, we used two different spatial averagers in each linear array, one for each branch of the split-drain MAGFET. This had the effect of averaging the current flowing in a branch of each MAGFET with the branches on the same side of the split drain of the other MAGFETs.

Spatial Averager
Figure 2. Spatial Averager

Looking at the figure, each node labeled A', B', and C' (this is a simple 3 MAGFET case) was connected to one of the split drain branches of a MAGFET, and the nodes labeled A, B, and C were connected to some circuit that was capable of sourcing current. The nMOS transistors in the schematic serve as pass transistors.

The vertical transistors allow current to flow from node A to A', and the horizontal transistors allow current sharing between MAGFETs. We can control the amount of sharing and thus the degree of averaging by controlling the gate voltage on the horizontal transistors, Vhoriz_bias and we can control the current flow from A to A' by controlling the gate voltage on the vertical transitors, Vvert_bias.

Spatial Averager Currents
Figure 3. Spatial Averager Current

Using SPICE, we ran some simulations on our spatial averager. We had four nodes, A, B, C, and D. We set V_vert_bias to an above-threshold voltage of 2V, attached current sources to nodes A, B, C, and D that sourced representative currents in the nA range. By varying the voltage on Vhoriz_bias and measuring the current flowing through nodes A', B', C', and D', we were able to get a first-pass look at the performance characteristics of our spatial averager.

Unsurprisingly, a low gate voltage on the horizontal pass transistor didn’t allow much current to flow between "channels." At a voltage significantly above threshold, all of the currents averaged out to a common value. We were satisfied with the results, and we brought Vhoriz_bias out to a pin so we could tweak it as necessary during experimentation. We also brought V_vert_bias out to a pin for the same reason.

Latching Comparator

Now that we have a way of dealing with some of the noise, we need to convert the analog current value in each branch of the MAGFET to a binary value that encodes which branch of the split drain carries most of the current.

Figure 4. Latching Comparator

To do this, we used a latching comparator, as seen in the figure. At its core, it’s a pair of cross-coupled inverters, which from a state-holding element, or staticizer. The node marked "Left" is attached to the left branch of a MAGFET, and the node marked "Right" is—unsurprisingly—attached to the right branch of the same MAGFET. When the clock signal, Clk, is low, the nMOS foot transistor is off, allowing the "Left" and "Right" nodes to float. The pMOS pullup transistors are on when Clk is low, so they pull nodes "Left" and "Right" up to Vdd.

When Clk goes high, the foot transistor turns on, and the pullup transistors turn off, allowing the staticizer to operate normally. The trick here is the MAGFET will start pulling both the "Left" and "Right" nodes down to GND, but because there’s a magnetic field, the current will favor one of the branches, causing one of the nodes to be pulled down faster.

Eventually, the difference in voltage between "Left" and "Right" will cause the staticizer to latch into a stable state. The staticizer state gives us a single bit that encodes which branch carries more current. By choosing which side of the statizicer to read the state from, we can choose what a 1 or 0 means (whether a 1 means more left-side current or the other way around).

Shift Register

Now that we have values for each MAGFET in each array, we need a way of getting the values off chip. Since we’re limited by the number of pins, we chose to do this serially. We read the bits from each latching comparator into a shift register. We then clock out the data stored in the shift register off chip.

To make things easy, we used a multiplexer to select what value gets shifted into each bit position in the register. One input is the input from the comparator, and the other is from the previous bit in the register. This allows us to minimize the amount of circuitry required to get the data off chip.