I took this course in the Fall of 2009 with Professor Rajit Manohar. During the Fall of 2011, Professor Manohar also conducted an informal lecture-format seminar covering similar topics. My handwritten notes for that seminar as are also available here.


Top-down approach to asynchronous design and the relation between computer architecture and VLSI design. For the asynchronous design component: high-level synthesis, design by program transformations, and correctness by construction. Topics include delay-insensitive design techniques, description of circuits as concurrent programs, circuit compilation, and correct design decomposition. Students will complete a group design project.
— Course Website


Our final project was to build an asynchronous system at the PRS level. We implemented the Empty Pipeline Detection Counter used in the 2010 ASYNC Paper Static Power Reduction Techniques for Asynchronous Circuits.

An Asynchronous Constant-Time Counter for Empty Pipeline Detection. Jonathan Tse and Derek Lockhart.