From JonWiki
Papers
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Proceedings
2010
- Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. Static Power Reduction Techniques for Asynchronous Circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems, May 2010.
Power gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two representative techniques, Cut-Off and Zig-Zag Cut-Off, and find that they offer an average of 80% and 20% in power savings, respectively, for asynchronous circuit families. We also present a new zero-delay (ZDRTO) wakeup technique for power gated asynchronous pipelines, which leverages the robustness of asynchronous circuits to delays and supply voltage variations. Our ZDRTO technique offers a tradeoff between wakeup time and static power reduction, making it suitable for power gating pipelines with low-duty cycle, bursty usage patterns.
- Abstract - PDF - Slides - DOI
Project Reports
2009
- Jonathan Tse and Derek Lockhart. An Asynchronous Constant-Time Counter for Empty Pipeline Detection.
Leakage losses have become a significant portion of power consumption in nanoscale circuits. Power gating techniques are effective in mitigating these losses, especially for low duty cycle systems and pipelines. It is of particular importance to determine whether a pipeline is empty before power gating it. If tokens are still in flight and useful computation is still being performed, preemptively shutting off a pipeline could destroy state, data, and execution correctness. We propose an asynchronous constant-time counter for use in empty pipeline detection, assuming the power savings from power gating the pipeline amortize the additional power consumption of the counter.
- Abstract - PDF
- Saugata Ghose and Jonathan Tse. Memory-Aware DVFS for CMP Systems.
High-performance processors are becoming increasingly power bound with technology scaling. Dynamic voltage and frequency scaling (DVFS) has emerged as an efficient method of reducing power consumption by lowering the operating voltage and frequency of a processor. We propose a multicore memory-aware DVFS scheme based on VSV, a uniprocessor DVFS algorithm that throttles a core based on L2 cache misses. The key observation is that during L2 misses, there may be periods during which the processor pipeline is stalled, waiting for data. These stalls offer an excellent opportunity for power savings with DVFS. Care must be taken, however, to be sure that the pipeline is actually stalled during an L2 miss and that the processor has sufficient work to complete when transitioning out of low-power mode. Using SPEC2K benchmarks, we evaluate both single-core and multicore VSV over a range of DVFS transition latencies: 12ns, 100ns, and 8.9us which are representative of different voltage regulator configurations. We show that fast-switching, on-chip voltage regulators for DVFS are necessary to see benefits using the energy delay squared metric. However, if low latencies--on the order of 12ns--are indeed possible, we show power benefits of 28%, performance costs of 35%, and improvements of 28% for a quad-core CMP. Increasing the latency to 100ns shows power savings of 45% at 45% performance loss, and additionally an energy delay squared degradation of 28%, though this is the result of poor prediction of instruction-level parallelism--8.9us latencies proved to be entirely infeasible.
- Abstract - PDF
2006
- Jonathan Tse, Eric VanWyk, and James Whong. Path Planning with Phased Array SLAM and Voronoi Tessellation.
Autonomous vehicles must often navigate environments that are at least partially unknown. They are faced with the tasks of creating a coordinate system to localize themselves on, identify the positions of obstacles, and chart safe paths through the environment. This process is known as Simultaneous Localization and Mapping, or SLAM. SLAM has traditionally been executed using measurements of distance to features in the environment. We propose an angle based methodology using a single phased array antenna and DSP aimed to reduce this requirement to a signal path for each data type. Additionally, our method makes use of rudimentary echo-location to discover reflective obstacles. Finally, our method uses Voronoi Tessellation for path planning.
- Abstract - PDF - DOI
- Jonathan Tse and Eric VanWyk. Network Survivability using Delaunay Triangulation.
Delaunay triangulations are used to establish local topology for mobile wireless networks using directional antennae The maximization of the minimum angle inherent to the Delaunay triangulations is exploited to minimize cross talk, which in turn assures that each individual link can operate at its peak bandwidth. Additionally, the use of mobile relay stations is examined to improve data rate. These mobile relays move themselves into optimal position using information from the Delaunay triangulation and seek to mitigate unavoidably bad node placements that are dictated by the network's users.
- Abstract - PDF
2005
- Jonathan Tse. A Primer on Forward Kinematics and the Jacobian Transform.
A short paper describing forward kinematics and applying the Jacobian Transform in control algorithms.
- Abstract - PDF
- Jonathan Tse. TUCAN Problem.
A short paper covering the canonical two cans draining serially problem from a differential equations standpoint.
- Abstract - PDF