ECE4750

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Contents

Overview

I took this course in the Fall of 2008 with Professor Edward Suh

Course Websites

Description (from the Syllabus)

This course covers today's high-end microprocessor-based computer architectures. We discuss technology trends, performance measurement, instruction set principles, pipelining, out-of-order execution, speculation, instruction-level parallelism, caches, virtual memory, compiler optimizations, simultaneous multithreading, multiprocessing and multicore architectures, and input/output.

ECE 475/CS 416 is a Culminating Design Experience (CDE) course. The project component of this course involves the design of a superscalar microprocessor with a cache subsystem at the register-transfer level (RTL).

Course Notes

01 - Introduction
02 - Cost and Performance
03 - Pipelining I
04 - Pipelining II
05 - Caches I
06 - Caches II
07 - Virtual Memory
08 - Dynamic Scheduling (Scoreboard)
08 - Scoreboard Detailed Example
09 - Dynamic Scheduling (Tomasulo)
09 - Tomasulo Detailed Example
10 - Branch Prediction
11 - Speculative Execution
12 - Speculative Execution II
13 - Multiple Issue
14 - Compiler Support
15a - The Future of Photonics
15b - System Level Architecture
16 - Multiprocessor Intro
17 - Memory Model
18 - Cache Coherence